cassdlcm/vmc_rs
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custom message parsing errors #1

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cassdlcm merged 22 commits from custom_errors into main 2023-12-31 19:36:26 +01:00
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1 changed files with 5 additions and 5 deletions
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Showing only changes of commit 20142c6922 - Show all commits

10
src/lib.rs
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@ -707,15 +707,15 @@ impl MessageBehavior for VmcExtMidiCcBit {
args, args,
}; };
} }
fn from_osc_message(msg: OscMessage) -> Result<Self, String> { fn from_osc_message(msg: OscMessage) -> Result<Self, FromMessageErr> {
if msg.args.len() != 2 { if msg.args.len() != 2 {
return Err(String::from("arg count invalid")); return Err(FromMessageErr::ArgCount(ArgCountErr { expected_in: vec![2], actual: msg.args.len(), addr: msg.addr}));
} }
let knob: i32; let knob: i32;
let active: bool; let active: bool;
match msg.args[0] { match msg.args[0] {
OscType::Int(i) => knob = i, OscType::Int(i) => knob = i,
_ => return Err(String::from("arg type invalid")), _ => return Err(FromMessageErr::ArgType(ArgTypeErr { expected: OscType::Int(0), actual: msg.args[0], addr: msg.addr, arg_count: 0})),
} }
match msg.args[1] { match msg.args[1] {
OscType::Int(i) => { OscType::Int(i) => {
@ -724,10 +724,10 @@ impl MessageBehavior for VmcExtMidiCcBit {
} else if i == 1 { } else if i == 1 {
active = true; active = true;
} else { } else {
return Err(String::from("arg value invalid")); return Err(FromMessageErr::IntRange(IntRangeErr { expected_lower: 0, expected_upper: 1, actual: i, addr: msg.addr, arg_count: 1}));
} }
} }
_ => return Err(String::from("arg type invalid")), _ => return Err(FromMessageErr::ArgType(ArgTypeErr { expected: OscType::Int(0), actual: msg.args[1], addr: msg.addr, arg_count: 1})),
} }
return Ok(VmcExtMidiCcBit { knob, active }); return Ok(VmcExtMidiCcBit { knob, active });
} }